Research Article
Dynamic delta sigma ADC with variable clock on 65 nm CMOS
Pitonak, Killat 2023
Publisher : IEEE
Published in: 2023 Kleinheubach Conference
This paper describes a dynamic delta-sigma ADC with a continuous-time modulator, FIR filters, and clock frequency control. Implemented in 65 nm CMOS at 1.2 V, the digital processing is done on an FPGA. The results highlight the effect of clock frequency switching on performance.